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Hardware Architecture

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Total of 23 entries
Showing up to 25 entries per page: fewer | more | all

Fri, 21 Jun 2024 (showing 6 of 6 entries )

[1] arXiv:2406.14263 [pdf, html, other]
Title: Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
Michele Caon (1), Clément Choné (2), Pasquale Davide Schiavone (2), Alexandre Levisse (2), Guido Masera (1), Maurizio Martina (1), David Atienza (2) ((1) Politecnico di Torino, (2) École Polytechnique Fédérale de Lausanne (EPFL))
Comments: 14 pages, 12 figures, submitted to IEEE Transactions on Emerging Topics in Computing
Subjects: Hardware Architecture (cs.AR)
[2] arXiv:2406.14081 [pdf, other]
Title: COOK Access Control on an embedded Volta GPU
Benjamin Lesage, Frédéric Boniol, Claire Pagetti
Subjects: Hardware Architecture (cs.AR)
[3] arXiv:2406.14008 [pdf, html, other]
Title: AMC: Access to Miss Correlation Prefetcher for Evolving Graph Analytics
Abhishek Singh, Christian Schulte, Xiaochen Guo
Comments: 14 pages, 16 figures
Subjects: Hardware Architecture (cs.AR)
[4] arXiv:2406.13505 [pdf, other]
Title: Demonstration of low power and highly uniform 6-bit operation in SiO2-based memristors embedded with Pt nanoparticles
G. Kleitsiotis, P. Bousoulas, S. D. Mantas, C. Tsioustas, I. A. Fyrigos, G. Sirakoulis, D. Tsoukalas
Subjects: Hardware Architecture (cs.AR); Emerging Technologies (cs.ET); Applied Physics (physics.app-ph)
[5] arXiv:2406.13080 [pdf, html, other]
Title: An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips
Haocong Luo, Ismail Emir Yüksel, Ataberk Olgun, A. Giray Yağlıkçı, Mohammad Sadrosadati, Onur Mutlu
Subjects: Hardware Architecture (cs.AR); Cryptography and Security (cs.CR)
[6] arXiv:2406.12930 (cross-list from cs.LG) [pdf, html, other]
Title: Tender: Accelerating Large Language Models via Tensor Decomposition and Runtime Requantization
Jungi Lee, Wonbeom Lee, Jaewoong Sim
Comments: To appear at the 51st International Symposium on Computer Architecture (ISCA 2024)
Subjects: Machine Learning (cs.LG); Hardware Architecture (cs.AR)

Wed, 19 Jun 2024 (showing 5 of 5 entries )

[7] arXiv:2406.12421 [pdf, html, other]
Title: ROVER: RTL Optimization via Verified E-Graph Rewriting
Samuel Coward, Theo Drane, George A. Constantinides
Subjects: Hardware Architecture (cs.AR)
[8] arXiv:2406.12385 [pdf, html, other]
Title: Accelerating Graph-based Vector Search via Delayed-Synchronization Traversal
Wenqi Jiang, Hang Hu, Torsten Hoefler, Gustavo Alonso
Subjects: Hardware Architecture (cs.AR)
[9] arXiv:2406.12346 [pdf, other]
Title: Towards the Certification of Hybrid Architectures: Analysing Interference on Hardware Accelerators through PML
Benjamin Lesage, Frédéric Boniol, Kevin Delmas, Adrien Gauffriau, Alfonso Mascarenas Gonzalez, Claire Pagetti
Comments: 12th European Congress on Embedded Real Time Software and Systems (ERTS 2024), Jun 2024, Toulouse, France
Subjects: Hardware Architecture (cs.AR)
[10] arXiv:2406.12774 (cross-list from cs.LG) [pdf, html, other]
Title: Towards Exact Gradient-based Training on Analog In-memory Computing
Zhaoxian Wu, Tayfun Gokmen, Malte J. Rasch, Tianyi Chen
Comments: 10 pages, 5 figures,2 tables
Subjects: Machine Learning (cs.LG); Hardware Architecture (cs.AR); Optimization and Control (math.OC)
[11] arXiv:2406.12110 (cross-list from cs.CR) [pdf, html, other]
Title: Cancellable Memory Requests: A transparent, lightweight Spectre mitigation
Hossam ElAtali, N. Asokan
Subjects: Cryptography and Security (cs.CR); Hardware Architecture (cs.AR)

Tue, 18 Jun 2024 (showing 4 of 4 entries )

[12] arXiv:2406.10627 [pdf, html, other]
Title: Triangel: A High-Performance, Accurate, Timely On-Chip Temporal Prefetcher
Sam Ainsworth, Lev Mukhanov
Comments: To be published at ISCA 2024
Subjects: Hardware Architecture (cs.AR)
[13] arXiv:2406.10491 [pdf, html, other]
Title: FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design
Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
Comments: 15 pages, 10 figures
Subjects: Hardware Architecture (cs.AR)
[14] arXiv:2406.10816 (cross-list from cs.PL) [pdf, html, other]
Title: Optimization of Armv9 architecture general large language model inference performance based on Llama.cpp
Longhao Chen, Yina Zhao, Qiangjun Xie, Qinghua Sheng
Subjects: Programming Languages (cs.PL); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR); Performance (cs.PF)
[15] arXiv:2406.10511 (cross-list from cs.DC) [pdf, html, other]
Title: High-Performance Hardware Accelerator with Medium Granularity Dataflow for SpTRSV
Qian Chen, Xiaofeng Yang, Shengli Lu
Subjects: Distributed, Parallel, and Cluster Computing (cs.DC); Hardware Architecture (cs.AR); Performance (cs.PF); Numerical Analysis (math.NA)

Mon, 17 Jun 2024 (showing 4 of 4 entries )

[16] arXiv:2406.09804 [pdf, html, other]
Title: Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms
Steven Colleman, Arne Symons, Victor J.B. Jung, Marian Verhelst
Comments: Accepted to ISQED2024
Subjects: Hardware Architecture (cs.AR)
[17] arXiv:2406.09677 (cross-list from cs.NE) [pdf, html, other]
Title: SAGA: Synthesis Augmentation with Genetic Algorithms for In-Memory Sequence Optimization
Andey Robins, Mike Borowczak
Comments: 6 pages, 2 Figures, 3 Tables
Subjects: Neural and Evolutionary Computing (cs.NE); Hardware Architecture (cs.AR)
[18] arXiv:2406.09606 (cross-list from cs.LG) [pdf, html, other]
Title: Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
Zongyue Qin, Yunsheng Bai, Atefeh Sograbizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong
Comments: 14 pages, 8 figures. arXiv admin note: text overlap with arXiv:2305.10838
Subjects: Machine Learning (cs.LG); Artificial Intelligence (cs.AI); Hardware Architecture (cs.AR)
[19] arXiv:2406.09535 (cross-list from cs.LG) [pdf, html, other]
Title: CircuitVAE: Efficient and Scalable Latent Circuit Optimization
Jialin Song, Aidan Swope, Robert Kirby, Rajarshi Roy, Saad Godil, Jonathan Raiman, Bryan Catanzaro
Comments: Design Automation Conference (DAC) 2024; the first two authors contributed equally
Subjects: Machine Learning (cs.LG); Hardware Architecture (cs.AR)

Fri, 14 Jun 2024 (showing 4 of 4 entries )

[20] arXiv:2406.09233 [pdf, html, other]
Title: C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
Luca Collini, Siddharth Garg, Ramesh Karri
Comments: Accepted at The First IEEE International Workshop on LLM-Aided Design
Subjects: Hardware Architecture (cs.AR)
[21] arXiv:2406.09208 [pdf, html, other]
Title: Python-based DSL for generating Verilog model of Synchronous Digital Circuits
Mandar Datar, Dhruva S. Hegde, Vendra Durga Prasad, Manish Prajapati, Neralla Manikanta, Devansh Gupta, Janampalli Pavanija, Pratyush Pare, Akash, Shivam Gupta, Sachin B. Patkar (Indian Institute of Technology Bombay)
Comments: 9 pages, 13 figures
Subjects: Hardware Architecture (cs.AR)
[22] arXiv:2406.09104 [pdf, html, other]
Title: A nA-Range Area-Efficient Sub-100-ppm/{\deg}C Peaking Current Reference Using Forward Body Biasing in 0.11-$\mu$m Bulk and 22-nm FD-SOI
Martin Lefebvre, David Bol
Comments: 14 pages, 28 figures
Subjects: Hardware Architecture (cs.AR)
[23] arXiv:2406.09078 [pdf, html, other]
Title: ONNX-to-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
Federico Manca, Francesco Ratto, Francesca Palumbo
Comments: Proceedings of the XXIV International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), June 29 - July 4, 2024. arXiv admin note: text overlap with arXiv:2309.13321
Subjects: Hardware Architecture (cs.AR)
Total of 23 entries
Showing up to 25 entries per page: fewer | more | all